用FPGA实现的位同步电路

位同步电路在现代通信中占有重要地位.根据数字信号特点,设计了超前-滞后全数字锁相环,采用现场可编程逻辑器件(FPGA)进行了集成处理,并通过了系统仿真和下载测试.测试结果表明,该设计方法能比较准确地恢复位同步信号,并适合在不同的传输速率下工作.

Design of Bit Synchronizing Circuit by Using FPGA

Bit synchronizing circuits are very important in modern communication. According to the characteristics of digital signals , an all digital early-late phase locked loop (PLL) is designed, field programmable gate array (FPGA) is used for its integration, a system simulation and download test are made. The test result shows that the bit synchronizing signals could be restored accurately by using the design method, which is appropriate for operation under the different transmission rates.