| 用D触发器构成的同步时序逻辑电路设计新方法 |
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| 引用本文： | 宋效先,王小平.用D触发器构成的同步时序逻辑电路设计新方法[J].河北北方学院学报(自然科学版),2007,23(2):13-16. |
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| 作者姓名： | 宋效先 王小平 |
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| 作者单位： | 河北北方学院医学信息与管理系,河北,张家口,075000;东北大学秦皇岛分校计算机工程系,河北,秦皇岛,066004 |
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| 摘 要： | 提出一种针对用D触发器构成同步时序逻辑电路的设计新方法,该方法可以直接从时序电路的状态转换图(STD)上获得D触发器的驱动方程,从而可以快速、准确地设计同步时序逻辑电路.
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| 关 键 词： | D触发器 同步时序逻辑电路 状态转换图 |
| 文章编号： | 1673-1492（2007）02-0013-04 |
| 修稿时间： | 2007-03-15 |
A New Designing Method of Synchronous Sequential Logic Circuits in D Flap-flop |
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| SONG Xiao-xian,WANG Xiao-ping.A New Designing Method of Synchronous Sequential Logic Circuits in D Flap-flop[J].Journa of Hebei North University:Natural Science Edition,2007,23(2):13-16. |
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| Authors: | SONG Xiao-xian WANG Xiao-ping |
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| Institution: | 1. Department of Medical Information Management, Hebei North University, Zhangjiakou 075000, Hebei, China; 2. Department of Computer Engineering, Northeast University at Qinhuangdao, Qinhuangdao 066004, Hebei, China |
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| Abstract: | A new designing method of synchronous sequential logic circuits in D flip-flop is proposed. This method is that excitation equation for D flip-flop is obtained directly from the state transition diagrams of sequential logic circuits, so the synchronous sequectial logic circuit is designed to a nicety. |
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| Keywords: | D flip-flops synchronous sequential logic circuits state transition diagram |
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