| 基于FPGA的GPS接收机的核心模块设计 |
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| 引用本文： | 张琦.基于FPGA的GPS接收机的核心模块设计[J].仲恺农业技术学院学报,2008,21(4):45-49. |
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| 作者姓名： | 张琦 |
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| 作者单位： | 仲恺农业工程学院,信息学院,广东,广州,510225 |
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| 摘 要： | 运用QuartusII对GPS接收机进行了数据采集（COM—R）、存储器（memory）、写地址控制（writer）、接收数据处理（reader）等核心模块的FPGA设计和仿真，结果表明各模块设计合理．
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| 关 键 词： | GPS接收机 捕获 跟踪 FPGA |
The core module of GPS receiver based on FPGA |
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| ZHANG Qi.The core module of GPS receiver based on FPGA[J].Journal of Zhongkai Agrotechnical College,2008,21(4):45-49. |
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| Authors: | ZHANG Qi |
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| Institution: | ZHANG Qi (College of Information, Zhongkai University of Agriculture and Engineering, Guangzhou 510225, China) |
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| Abstract: | Quartus II was used to for FPGA designing and simulating in data acquisition(COM-R),memory(memory),write address control(writer),and received data processing(reader) of core modules of GPS receiver.The simulation results indicated that the module designs were reasonable and correct. |
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| Keywords: | GPS receiver capture tracking FPGA |
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