Self-aligned,vertical-channel,polymer field-effect transistors |
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Authors: | Stutzmann Natalie Friend Richard H Sirringhaus Henning |
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Affiliation: | Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE, UK. |
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Abstract: | The manufacture of high-performance, conjugated polymer transistor circuits on flexible plastic substrates requires patterning techniques that are capable of defining critical features with submicrometer resolution. We used solid-state embossing to produce polymer field-effect transistors with submicrometer critical features in planar and vertical configurations. Embossing is used for the controlled microcutting of vertical sidewalls into polymer multilayer structures without smearing. Vertical-channel polymer field-effect transistors on flexible poly(ethylene terephthalate) substrates were fabricated, in which the critical channel length of 0.7 to 0.9 micrometers was defined by the thickness of a spin-coated insulator layer. Gate electrodes were self-aligned to minimize overlap capacitance by inkjet printing that used the embossed grooves to define a surface-energy pattern. |
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