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基于FPGA串并结合FIR滤波器的设计
引用本文:于亚萍,陈雪强,刘源,卫勇. 基于FPGA串并结合FIR滤波器的设计[J]. 湖北农业科学, 2012, 51(14): 3092-3095
作者姓名:于亚萍  陈雪强  刘源  卫勇
作者单位:1. 天津农学院机电工程系,天津,300384
2. 河南省济源市金马焦化有限公司,河南济源,454650
基金项目:国家星火计划项目(2010GA 610018);天津农学院科学研究发展基金项目(2011N04)
摘    要:根据FIR滤波器的特性和分布式(DA)算法的特点,基于FPGA实现FIR滤波器的原理和方法,在拆分查找表的基础上,利用串并结合DA算法对数字滤波器的设计进行优化,设计更高阶次的滤波器并节省所占用的硬件资源.采用串并结合DA算法设计了16阶FIR低通滤波器,在Quartus Ⅱ 7.0下进行仿真,结果验证了该方法滤波效果好,能够有效地减少FPGA硬件资源的使用,提高FIR的运算速度.

关 键 词:FIR滤波器  查找表  FPGA  分布式(DA)算法

Design of FPGA-Based Serial-Parallel FIR Filter
YU Ya-ping , CHEN Xue-qiang , LIU Yuan , WEI Yong. Design of FPGA-Based Serial-Parallel FIR Filter[J]. Hubei Agricultural Sciences, 2012, 51(14): 3092-3095
Authors:YU Ya-ping    CHEN Xue-qiang    LIU Yuan    WEI Yong
Affiliation:1(1.Department of Mechanic and Electronic Engineering,Tianjin Agricultural University,Tianjin 300384,China; 2.Jinma Coking Limited Company,Jiyuan City of Henan Province,Jiyuan 454650,Henan,China)
Abstract:According to the characteristics of FIR filter and distributed algorithm(DA),the theory and method of FIR Filter was realized using DA based on FPGA.On the basis of table partitioning,the designation of FIR filters was optimized by serial-parallel arithmetic aiming at filters with higher order while saving the hardware it would use.16-order FIR filters was designed by serial and parallel DA and simulated in Quartus Ⅱ 7.0.Results showed that the FIR filters were with small resource usage and high speed compared with traditional methods.
Keywords:FIR filter  look-up table  FPGA  distributed algorithm
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