Eliminate the glitch in design of CPLD/FPGA

Complex Programmable Logic Device(CPLD) and Field Programmable Gate Array(FPGA) play more and more important roles in design of modern digital system. But sometimes, the glitch in design of the system become handicap of succeedable design. This paper analyses the cause, judge and locate of glitch in design of modern digital system apply the component of CPLD/FPGA. Three methods about eliminate the glitch make use of EDA tools are discussed and some examples are given.     

Realizing Key Schedule of Rijndael Algorithm Integrating with Chaos

Encryption is an important method which is used to protect the information of an individual and enterprises and the secret of nations. Rijndael algorithm is the new advanced encryption standard, and has extensive application foreground because of its much merit. Modem encryption algorithms are based on keys. However, so far few of people research into the key schedule of rijndael algorithm and especially do research on the generation of its initial keys. This paper researches into the mapping of Logistic, makes use of a chaos algorithm to produce initial encryption keys because it can create chaos sequences of high randomicity. Further more, corresponding CPLD implementation is given.     

CPLD/FPGA Programmable Logic Devices'' In System Reconfiguration Method

This article has discussed the methods of configuring the CPLD/FPGA devices based on SRAM, and choose the microprocessor to configure the FLEX10k devices of ALTERA. From the article ,we can see that this low cost and easy done method can enable the system to configure the CPLD/FPGA devices automatically as soon as the system is re set or power is re added to it. It has solved the problem that CPLD/FPGA devices based SRAM may lose it's logic function when dropped out of power, and it enables the single chip to have several functions.     

MPEG Layer Ⅲ Decoder Design Based on DSP

The design of MP3 decode system based on DSP is introduced. TLV320AIC23, a high performance and stereo codec chip, is selected as a D/A converter in the system. Two McBSPs ofDSP are connected to TLV320AIC23, one of them acts as configuration interface, the other ,the audio digital interface. Configuration interfacemode is SPI. The MP3 audio bitstreamtransmissionbetween the PC and DSP isrealized through the USB1.1 interface. So it is convenientto access MP3 audio bitstream. A large capacitymemory device, Compact Flash Card , is a storage media accessing MP3 bitstream.a programmable logical device, CPLD, controls reading, writing and chip selection of USB and Compact Flash Card. Some experiments show the systemcan well accomplish MP3 decodingand playing.     

红花草莓红花基因RAPD标记转化为SCAR标记

红花草莓不但具有经济价值,还具有很高的观赏价值。本研究将3个与红花基因连锁的RAPD标记即AW65679（1031bp）、S484（620bp）与S1383（500bp）进行了克隆与核苷酸测序,并根据测序结果设计4对SCAR引物,将这4对引物对红花草莓品种粉红熊猫、白花草莓品种鬼怒甘及它们的杂交后代进行PCR扩增程序优化和鉴定,筛选出一对SCAR引物可扩增出与红花基因连锁的特异片段AW65679（1038bp）,这就是与红花基因连锁的SCAR标记。SCAR标记因其稳定性好,重复性高将为草莓分子育种开辟一条新的有效途径。     

A Comprehensive Evaluation Method for Uniformly Distributed Random Numbers

Mathematical methods for generating uniformly distributed U(0,1) random numbers are described.A comprehensive evaluation method for uniformly distributed random numbers is presented.This method is used to evaluate the randomness of uniformly distributed random sequences generated by software.Some good seeds have been selected out that can be used to generate uniformly distributed random sequences with better performance.     

Complex Programmable Logic Devices Implementation of FFT Processor

In order to accelerate the working speed of a FFT processor, this paper presents a hardware structure of a FFT processor, which is suitable for CPLD , and the 128-point FFT single-chip processor is realized by means of FLEX10K CPLD and MAX+PLUS II software. The calculation time of the processor is less than 230uS. The research proves that the combination of CPLD and FFT increases the working speed of FFT processors and raise the level of application .     

Practical Method of High-Speed Access for Medical Digital Image Sequences

The high-speed access for medical digital image sequences was restricted to special device and complicated system in the past. The authors present a new method of high-speed access for medical digital image sequences which can be performed on general computer by means of the combination of Serial ATA(SATA) and Redundant Array of Independent Disk(RAID).Then they introduce the scheme of system configuration and software program. Lastly the testing result is given and the speediness,cheapness and conveniency of this method are elucidated.     

Circuit Design of Piezoelectric Biosensor Based on CPLD

A kind of sampling circuits of piezoelectric biosensor is designed based on the CPLD devices. It is realized that 10 MHz high frequency signal measure and sampling, data display and data serial communication etc. The system has been proved to have high reliability, good real-time performance. The system architecture are discussed in detail including hardware and software, and the implementation. The simulation result of CPLD kernel and the frequency curve by sample soft are shown.     

Rise Time Measurement System of Steep Pulse Based on Frequency Difference Multiply Technology

To accurately measure the ascendant time of a high-voltage steep pulse, the pace and precision of counter is highly challenged. The authors put forward the design of high-speed count system based on CPLD and DSP. In this system, the outer crystal oscillator of CPLD act as low-frequency clock whose frequency division and phase invertion are done by D-trigger group designed with CPLD, and finally,they get the counter with 200 MHz i. e. 5ns per period by the method of frequency difference multiply. The counting pace and precision are promoted, and meet the demand to measure the ascendant time of high-voltage steep pulse. It can be extended to measure the descendant time of pulse, pulse width and periods.     

Automatic Testing Method Based on All Duality Algorithms

What is the most important in automatic testing is automatically generating test cases and then filter them,which involve parameters' combination and filter.The authors do an argumentation by using all duality algorithms to(imply) the generating and automatically filter,and then assume an automatic testing way,prove the feasibility of this way with an instance.An additional basic testing shows that the algorithm is satisfactory.     

Research on Bridge Structure Noise of Railroads and Underground

This paper analyses the generating mechanism of radiation noise which produced by bridge structures and vibro-acoustic characteristics, and reviews the current situation of the researches on the relevant standards of structure noise at house and abroad. The author summarizes the method of measurement and calculation about structural noise at house and abroad, further notes their limits. This paper explores the impact of such factors as rain speed and other different fluids on structure noise. The noise characteristics of structures like cavity structure and thin-slab structure are also discussed. Strategies for reduce the bridge structure noise are summed up by reducing the vibration of track structure, altering the structure of boundary conditions, increasing the stiffness and changing the bridge cross section. Finally it comes to a conclusion that a combination of these strategies is the root way to settle the question of the bridge structure noise.     

草果无公害烘干设备及工艺的效益分析

指出传统烘烤方式干燥草果所存在的弊端。就新开发的5HX-45型烘干设备及配套的草果烘干工艺,与传统的烘烤方法进行详细的经济及社会效益对比分析。     

谷物真菌毒素溯源系统初探

主要探讨了谷物制品中真菌毒素类溯源系统构建的基本原理以及模式,包括构建分级溯源点的方式,设计各溯源点的主要功能以及具体详尽的实现流程。在部分关键环节,将胶体金免疫层析检测技术运用于其中,建立以快速检测为技术核心的食品溯源系统,对于控制食品质量安全、促进食品国际贸易具有重大的现实意义。     

Data Acquisition System of PCI Bus Interface

After having studied the PCI bus and compared the capability, it is analyzed and compared in capability and cost and complexity of some kinds of application for data acquisition system, a high speed system which composed of chip S5933 and CPLD is designed.     

Optimizing Algorithm for Disassembly Sequence Based on Tabu Search and Genetic Algorithms

In order to optimize disassembly sequence about wornout or malfunctioning products,firstly,it is proposed to build Interference-Freeness Matrix for describing the structure of assembly.Secondly,computing model of automatic generating and optimizing disassembly sequence of assembly is proposed based on Genetic Algorithms.Then,after inputing some disassembly sequences and other controlling parameters,the program can search optimizing disassembly(sequences) valid in geometry.Minimal reorientation number of times during disassembling assembly is assigned as optimizing objective.At last,because the neighborhood may converge too fast and limit the search to a local optimum prematurely during the process of Genetic Algorithms(GAs),the authors combine the strengths of GAs and Tabu search and presented the detailed flow chart of the hybrid approach.More robust search behavior can possibly be obtained by incorporating the(Tabu's) intensification and diversification strategies into GAs.The details of the hybrid approach and a case study are presented here.Much engineering examples is tested to demonstrate the approach.The results given show that the valid disassembly sequences obtained are superior to those derived from GAs alone in fitness value,number and distribution.     

Digital Filtering with Zero Phase Error

Aiming at the problem of phase error caused by normal filters in signal processing , summarizes the important meaning of digital filtering with zero phase error. Puts forward RRF Filtering which is a new way to realize digital filtering with zero phase error through reversing the time serials of the signal. Another way to realize digital filtering with zero phase error is suggested through reversing the time serials of normal filter. Testifies the way to realize digital filtering with zero phase error. Points out how to design the digital filter with zero phase frequency peculiarity. Solves the problem of phase error in DSP.     

Method of Measuring Rotational Speed for a High-speed Rotator Dynamic-balancing Testing System Based on DSP

The device of testing rotational speed is very important to dynamic-balancing testing system.Requirements for the device of testing rotational speed include: high-accuracy,stabilization,credibility,and shorter testing time.To the development of high-speed rotor dynamic-balancing testing system based on DSP(digital signal processing),the way of picking-up rotator reference signal,testing rotator speed based on DSP and the design of software are introduced.This new way of testing rotational speed in high-speed rotor dynamic-balancing testing system based on DSP is accurate,simple,convenient,the range of rotational speed which can test is broad,and the new way is very suitable to pick-up the amplitude and phase of vibration caused by unbalanced amount.     

Design and Realize the Short Message Service System

Along with the widely using of mobile telephone, the SMS (Short Message Service) has achieved more and more approbation of consumers. Besides the point-point application of SMS among mobile phones, a new application of SMS between information system and mobile phones is developed quickly now, and it is a new way to achieve information conveniently and duly for users. In this paper, we design a software based on SMS to solve some problems which exists in the communication among employees. We also give out the system's functions, key technology and application in the enterprises. This system has some important value in theory and application for building a digital enterprise.