Rise Time Measurement System of Steep Pulse Based on Frequency Difference Multiply Technology

To accurately measure the ascendant time of a high-voltage steep pulse, the pace and precision of counter is highly challenged. The authors put forward the design of high-speed count system based on CPLD and DSP. In this system, the outer crystal oscillator of CPLD act as low-frequency clock whose frequency division and phase invertion are done by D-trigger group designed with CPLD, and finally,they get the counter with 200 MHz i. e. 5ns per period by the method of frequency difference multiply. The counting pace and precision are promoted, and meet the demand to measure the ascendant time of high-voltage steep pulse. It can be extended to measure the descendant time of pulse, pulse width and periods.     

Real-time Infrared Image Acquisitionand Processing System Based on PCI Bus

In the system of infrared imaging acquisition, it is necessary to improve data transfer to satisfy the characteristics of high speed and real time. So,this paper introduces PCI bus and PCI inerface to imaging acquisition. The protocol of data transfer of PCI local bus and the structure of PCI9050 are studied in detail, and the IRFPA data acquisition system are described based on the protocol of data transfer of PCI local bus. The system adopts frame buffer to make slow transmission between peripheral circuit and PCI bus.CPLD is also used as a master of logic time control?     

Data Acquisition System of PCI Bus Interface

After having studied the PCI bus and compared the capability, it is analyzed and compared in capability and cost and complexity of some kinds of application for data acquisition system, a high speed system which composed of chip S5933 and CPLD is designed.     

Study and Design on Teaching Experiment Instrument of CT Data Acquisition System Based on CPLD

The purpose of developing Teaching Experiment Instrument of CT is to demonstrate the whole process of CT scanning more intuitively, thereinto the design of data acquisition system is one of the emphases in the developing of the CT system. This paper mainly introduces the design and implement of the data acquisition system of CD - 50BG, using CPLD apparatus which have the characteristic of high integration, in the design of data acquisition system to achieve the target of minishing system bulk and improving system reliability. Aiming at the data loss of CD - 50BG during acquiring data, the data acquisition system is reformatively redesigned, the data loss in the high speed data acquisition process is reduced so that the stability of transmission has been improved by using FIFO.     

Study and Design on S5933 Special Chip Data Acquisition System Based on PCI Bus

The paper explains the data transfer mechanism based on the PASS-THRU channel of S5933, and gives a method to develop data acquisition system based on PCI bus, the problem of designing the PCI interface controller is avoided, saving time and cost of development production. The use of CPLD makes the stucture of the system more integrated. The 32-bit data acquisition system,the speed of data transmission is faster,the CPU resource and PCI bus resource are spared.     

Intelligent Sound Broadcast System of Bus Based on CPLD

The traditional sound broadcast system of bus makes use of MPU. It's shortcoming is have lower dependability, at the same time the maintenance and upgrade is difficult. In order to solve these problems, an intelligent sound broadcast system of bus makes use of Complex Programmable Logic Device(CPLD) and sound chip ISD2560 is introduced, and the principle of design is analysed. Because of the ability of In System Programmability of CPLD's JTAG, and take full advantage of the resource in CPLD, this system have no use for MPU. So, the hard circuit of this system is simple, and the system is easy to debug, upgrade and has very high dependability and better practicability.     

Eliminate the glitch in design of CPLD/FPGA

Complex Programmable Logic Device(CPLD) and Field Programmable Gate Array(FPGA) play more and more important roles in design of modern digital system. But sometimes, the glitch in design of the system become handicap of succeedable design. This paper analyses the cause, judge and locate of glitch in design of modern digital system apply the component of CPLD/FPGA. Three methods about eliminate the glitch make use of EDA tools are discussed and some examples are given.     

CPLD/FPGA Programmable Logic Devices'' In System Reconfiguration Method

This article has discussed the methods of configuring the CPLD/FPGA devices based on SRAM, and choose the microprocessor to configure the FLEX10k devices of ALTERA. From the article ,we can see that this low cost and easy done method can enable the system to configure the CPLD/FPGA devices automatically as soon as the system is re set or power is re added to it. It has solved the problem that CPLD/FPGA devices based SRAM may lose it's logic function when dropped out of power, and it enables the single chip to have several functions.     

Walsh Sequences Generation with Rademacher Functions and Its Digital Realization

This paper first discusses the application of Walsh sequences in the forward link and the reverse link of the IS-95 system. The advantages and disadvantages of each way generating Walsh sequences are analyzed. The theory and step of using Rademacher function to construct Walsh sequences is discussed especially. Then a way of generating Walsh sequences with CPLD is presented and the Design is described by VHDL on CPLD chip. This way mostly relays on digital logic operation, so it can be realized easily through digital circuit and it needs little memory unit. The result of emluator makes clear this way is feasible.     

Development of High Resolution Plane Measuring Instrument

In practical application, plane measuring instrument is mainly used to test flatness of workpiece in micro level, so that people can check if the workpiece is qualified or not. High resolution and high stabilization are two key technologies. The method of resolution extension is presented for improving the resolution of workpiece,and a signal source with high stabilization, which is designed by microcontroller and Complex Programmable Logic Device(CPLD), improves the stabilization of the system. The paper propose work principle and test step, the design of hardware,and introduces the measure for improving precision. The system is consisted of a position transducer, a signal source with high stabilization, a microcontroller and a signal processing unit. It has many advantages such as high resolution, high stabilization, low cost and simple operation, It also has been formally put to use in Chongqing Actaris Measurement Instrument Co.Ltd. now.     

Modal parameters identification for short data sequences based on stratified sampling and optimism complex Morlet wavelet

A novel modal parameter identification method based on stratified sampling and optimism complex Morlet wavelet is proposed for short data sequences. Stratified sampling is applied to divide the structure response signal into different layers which called sub samples with different thresholds, and then free decrement response signal of each layer is extracted by random decrement technique. The optimism complex Morlet wavelet transform is applied to identify modal parameter of each layer, and the weight of the layer is also determined based on the sample standard deviation. The modal parameter of the structure can be obtained by weighted calculation.The engineering application shows that the proposed method has the ability to identify modal parameter accurately, decouple low frequency intensive modal composition and restrain high frequency fake modal effectively.     

基于LabVIEW的潜油电泵数据采集系统

应用LabVIEW虚拟仪器现场可编程门阵列(FPGA)对潜油电泵的电压、电流参量进行实时数据采集,通过上位机对采样数据进行分析处理,得到潜油电泵的视在功率、有功功率、无功功率和功率因数,并与电能质量检测仪检测数据进行对照。系统硬件采用NI sbRIO-9606和NI9683夹层板配合使用,突破了传统的依靠DAQ助手的硬件采集,基于现场可编程门阵列(FPGA)的数据采集系统,由软件构成采集功能芯片,可控性强,准确性高,应用性好。实验表明,该系统在误差允许范围内能够对数据进行准确采集。     

Application Of Virtual Instrumentation in Radio Measuring System

Radio administration department permits station's building and distributes frequency used by measurement in radio electromagnetic environment. In order to improve the efficiency and accuracy of testing, the automatic measuring system software based on virtual instrumentation technology(VISA and SCPI) has developed at the VB platform, which changes the phase of outputting data just by printing spectrum chart .The system realizes functions of data sampling, transffering and processing in HP E7405A EMC analyzer. It also can establish database files for saving, inquirring, data shareing, exchanging and processing. The spectrum chart of mearsurment result is the same as that of result by manual work.     

Composite structure of sterilization and descaling system for circulating cooling water

In order to resolve the hazard of biofouling and scale in circulating cooling water system of power stations, this paper takes the lead in combining high voltage pulses and high frequency pulses for sterilization and descaling process. It analyzes both electromagnetic effects and biochemical effects on sterilizing and descaling process caused by the high voltage pulses and high frequency pulses respectively. The pulse generator is designed according to the requirements of electromagnetic parameters for effective operation. The design and improvement of process chambers are assisted by electromagnetic field simulation technology. Experimental data prove that the system can output high voltage pulse whose maximum peak value reaches 7 kV and high frequency pulse whose maximum peak value reaches 100 V the frequency ranges from 500 kHz to 2 MHz. The rate of sterilization can be as high as 91,and the rate of descaling reaches 71. This system is expected to achieve the standards of industrial water treatment through further research.     

MPEG Layer Ⅲ Decoder Design Based on DSP

The design of MP3 decode system based on DSP is introduced. TLV320AIC23, a high performance and stereo codec chip, is selected as a D/A converter in the system. Two McBSPs ofDSP are connected to TLV320AIC23, one of them acts as configuration interface, the other ,the audio digital interface. Configuration interfacemode is SPI. The MP3 audio bitstreamtransmissionbetween the PC and DSP isrealized through the USB1.1 interface. So it is convenientto access MP3 audio bitstream. A large capacitymemory device, Compact Flash Card , is a storage media accessing MP3 bitstream.a programmable logical device, CPLD, controls reading, writing and chip selection of USB and Compact Flash Card. Some experiments show the systemcan well accomplish MP3 decodingand playing.     

Design of Vision System Based on Service Robot

A vision system based on the service robot is involved. In the system, picture signal is acquired by the picture sensor OV7635. Frame memory AL422B is used as data buffer memory, while CPLD controlled the time order DSP performed. In the software system of image processing, to accomplish color image segmentation and recognition, the threshold vector judgment and improved seed-fill algorithm is introduced, and the image geometric moment is calculated during the segmenting. In order to achieve a vision servo system which composed of image-based feedback and adaptive compensation, the deduced matrix-based Jacobian from the image moment is taken as image feature. Adopted the TFT LCD is adopted to straightly disolav the result of vision recognition and vision tracing.     

Complex Programmable Logic Devices Implementation of FFT Processor

In order to accelerate the working speed of a FFT processor, this paper presents a hardware structure of a FFT processor, which is suitable for CPLD , and the 128-point FFT single-chip processor is realized by means of FLEX10K CPLD and MAX+PLUS II software. The calculation time of the processor is less than 230uS. The research proves that the combination of CPLD and FFT increases the working speed of FFT processors and raise the level of application .     

Portable ECG Monitor Front- ended Design with C8051 F020

The electrocardiogram (ECG) signal is a recording of the electrical activity on the body surface generated by the heart frequency of which is weak and low. Many researchers devote themselves to get more perfect ECG in many ways. This article introduces the characterize of an ECG signal , then discusses the requirements for the sampling circuit of an ECG. Since there are some shortcoming in common design means, the authors give an effective circuit. The system is composed of a low-cost , low-power and high-performance MCU C8051F020 , amplifier AD620 , right-leg drive circuit ,communication circuit and power management circuit. Then software design is given which is used to sampling and filtering ECG signal. Levkov filter arithmetic and smooth filter arithmetics are used in this design. In the end , the authors advance a distributing and networking ECG monitor system.     

用SSR技术和混合取样方法估算玉米群体间的遗传距离

The factors affecting the binding characteristics of GBSS with starch granule were studied using a wheat (Triticum aestivum) cultivar Chinese Spring with different temperature treatments. After sodium dodecyl sulfate polyacrylamide gel electrophoresis (SDS-PAGE) analysis, we got GBSS concentration by coomassie brilliant blue G-250(CBB G-250) method. The results showed that the temperature affected the binding of GBSS and starch granule. In 50–80℃, the concentration of GBSS unbound from starch increased with the temperature rising, which the maximal concentration was 11.361 μg mL^-1 at 80℃, while that was reduced when the temperature was 85–95℃. Furthermore, Mg²⁺ could also affect the quantity of GBSS unbound from starch. When Mg2+ concentration was lower than 1.75 mmol L^-1, the concentration of GBSS unbound increased. The lower Mg²⁺ concentration, the higher the concentration of GBSS unbound. However, when Mg²⁺ concentration was higher than 2.5 mmol L^-1, it could restrain GBSS unbinding. These results showed that GBSS bound starch granule by non-covalent bonds. The best GBSS extracting conditions were 55 mmol L^-1 Tris-HCl (pH 6.8), 0.75 mmol L^-1 MgCl₂, 2.3% SDS, 5% 2-ME and 10% glycerol, 15 min in boiling water, or 55 mmol L^-1 Tris-HCl (pH 6.8), 0.75 mmol L^-1 MgCl₂, 2.3% SDS, 5% 2-ME and 10% glycerol, 80℃ 30 min. The results are helpful to investigate 3-D structure of biological activated GBSS and mechanism of GBSS binding with starch granule.     

Design of the Expandable (I)FFT Implemented in the CPLD

The architecture of scalable length and high speed FFT processor based on CPLD(Complex Programmable Logic Device) is proposed, including the pipeline architecture of the radix mixed FFT algorithm, the address regularity of the read-then-write RAM, the array architecture of short-length FFT and the pipeline complement architecture of CORDIC(Coordinate Rotation Digital Computer) algorithm. If the input-data velocity is 20 MHz,the time expended on 1024-point FFT is 50 us.