| 一种新的可控分频器的FPGA实现 |
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| 引用本文： | 王世元,谢开明,石亚伟,陈孟钢,龙正吉.一种新的可控分频器的FPGA实现[J].西南农业大学学报,2007,29(1):89-93. |
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| 作者姓名： | 王世元 谢开明 石亚伟 陈孟钢 龙正吉 |
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| 作者单位： | 西南大学电子信息工程学院,重庆400715 |
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| 基金项目： | 西南师范大学科技基金资助项目（SWNUQ2005004）. |
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| 摘 要： | 基于双边沿检测技术获得时钟信号的倍频窄脉冲，利用该脉冲对时钟信号的双边沿计数，进而实现了时钟信号的整数和半整数分频．采用VHDL硬件描述语言和原理图输入方式，在QuartusⅡ平台下实现分频器的综合和仿真，并用ACEX1K30芯片实现．实验表明该方法的有效性和可靠性．
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| 关 键 词： | 分频器 双边沿检测 窄脉冲 |
| 文章编号： | 1000-2642（2007）01-0089-05 |
| 修稿时间： | 2006-02-24 |
Implementation of a New FPGA-Based Controllable Frequency Divider |
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| WANG Shi-yuan, XIE Kai-ming, SHI Ya-wei, CHEN Meng-gang, LONG Zheng-ji.Implementation of a New FPGA-Based Controllable Frequency Divider[J].Journal of Southwest Agricultural University,2007,29(1):89-93. |
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| Authors: | WANG Shi-yuan XIE Kai-ming SHI Ya-wei CHEN Meng-gang LONG Zheng-ji |
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| Institution: | School of Electronic and Information Engineering, Southwest University, Chongqing 400715, China |
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| Abstract: | This paper describes a new method for implementing a controllable frequency divider. The double frequency of the clock signal is achieved with the technique of double edge detection. By counting the double edges of the double frequency pulses, the integer or half-integer frequency divider is implemented. The frequency divider implemented with an ACEX1K30 chip is described in VHDL, and synthesized and simulated with QuartuslI. The results in an experiment confirmed the validity and reliability of the new method. |
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| Keywords: | frequency divider double edge detection narrow pulse |
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