| 层次化芯片设计中的Slew违规避障修正方法 |
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| 引用本文： | 杨磊,孙赛赛.层次化芯片设计中的Slew违规避障修正方法[J].山东农业大学学报(自然科学版),2012,43(2):271-275. |
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| 作者姓名： | 杨磊 孙赛赛 |
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| 作者单位： | 1. 山东农业大学信息科学与工程学院,山东泰安,271018
2. 泰山医学院信息工程学院,山东泰安,271016 |
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| 摘 要： | 芯片层次化物理设计给布局布线、时序收敛都带来了很大挑战。在顶层布局布线阶段,子模块相当于障碍物,当连线遇到较大障碍阻挡时,EDA工具不能够妥善处理,从而遗留较多Capacitance/Slew违规。本文从工程中遇到的实际问题出发,提出了一种Capacitance/Slew避障修正的方法,并在多个基于45 nm及65 nm工艺节点的专用集成电路项目上成功应用。实验结果表明,该方法能够快速修正因障碍导致的Capacitance/Slew违规,加快芯片上市时间。
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| 关 键 词： | 层次化物理设计 布局布线 避障 专用集成电路 |
OBSTACLE AVOIDING SLEW - FIX METHODOLOGY IN HIERARCHICAL PHYSICAL DESIGN OF ASICS |
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| YANG Lei
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SUN Sai-sai.OBSTACLE AVOIDING SLEW - FIX METHODOLOGY IN HIERARCHICAL PHYSICAL DESIGN OF ASICS[J].Journal of Shandong Agricultural University,2012,43(2):271-275. |
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| Authors: | YANG Lei SUN Sai-sai |
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| Institution: | 1.College of Information Science and Engineering,Shandong Agricultural University,Taian 271018,China; 2.School of Information & Engineering,Taishan Medical University,Taian 271016,China) |
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| Abstract: | Hierarchical physical design pose a big challenge to place and route in deep sub-micron ASIC designs,for the EDA tools having trouble to avoid the large obstacles on the top level.This paper proposes a method of obstacle avoiding slew-fix for hierarchical physical design.It has been already applied on several chips in 45nm and 65nm technology,the result shows it can help to achieve rapid time-to-market. |
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| Keywords: | Hierarchical physical design place and route obstacle avoiding ASIC |
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