High speed, high precision digital phase sensitive detector design for electrical impedance tomography

Electrical impedance tomography (EIT) system must have the properties of high precision and speed, thus the digital phase sensitive detector (DPSD) based on the field programmable gate array(FPGA) is developed for data collection of EIT. Based on the principle of DPSD, the relationship between signal to noise ratio (SNR) and sample resolution as well as total number of samples is deduced. An implementation scheme of this system and a method of designing analog to digital converter (ADC) clock based on direct digital synthesis (DDS) technology are provided. The system adopts high speed multi channel ADC and low jitter clock conditioner for ADC. Real time DPSD is implemented with FPGA. The experiments show that the measurement accuracy reaches 0.03% and the SNR reaches 85 dB. The agar phantom experiments prove that the performance of the DPSD meet the designing requirement for EIT.